1. Field of the Invention
The present invention relates to interposer substrates, and, more particularly, to an interposer substrate used in stacked packages and a method of fabricating the same.
2. Description of Related Art
With the advancement in semiconductor packaging technology, various types of packages of the semiconductor device have been developed, in order to increase electrical functionality and reduce packaging space. For instance, a Package on Package (PoP) is developed having multiple packaging structures stacked on one another. This type of package having the property of heterogeneous integration of a System in Package (SiP) incorporates and integrates various electronic components of different functions such as: memory, central processing unit, graphic processor, image processor etc., in a package through stacking, and is thus very suitable to be used in various low-profile electronic products.
Earlier stacked packages are formed by stacking memory packages (memory IC) over the logic packages (logic IC) via a plurality of solder balls. As the demand for light-weight and low-profile electronic products grows, the density of wiring on the memory package increases. The memory package is measured in nanometers, and the distances between the contact points are further shortened. However, the distances between the logic packages are measured in micrometers, and the logic packages cannot be miniaturized any further to comply with the distances between the memory packages. As a result, even a memory package with high density wiring is provided, there is no suitable logic package to go in concert with the memory package, thereby unable to achieve efficient production of the electronic products.
Accordingly, in order to overcome the above mentioned drawbacks, an interposer substrate is disposed between the memory package and logic package. For example, the bottom of the logic package is coupled to the logic package having logic chips with high distance, while the top terminal of the interposer substrate is coupled to a memory package having a memory chip of smaller distance.
FIG. 1 shows a schematic cross-sectional view of a conventional interposer substrate 1. The interposer substrate 1 comprises a first insulating layer 13, a first wiring layer 11, a plurality of first conductive pillars 12, a second wiring layer 14, a plurality of second conductive pillars 15, a second insulating layer 16, and surface processing layers 17,17′. The first insulating layer 13 has a first surface 13a and an opposing second surface 13b. The first wiring layer 11 is embedded in the first insulating layer 13 and exposed from the first surface 13a, for the chip mounting pads to be mounted thereon. The first conductive pillars 12 are formed in the first insulating layer 13 and the first wiring layer 11. The second wiring layer 14 is formed on the second surface 13b of the first insulating layer 13 and the first conductive pillars 12. The second conductive pillars 15 are formed on the second wiring layer 14. The second insulating layer 16 is formed on the second surface 13b of the first insulating layer 13 and encapsulates the second wiring layer 14 and the second conductive pillars 15, with a portion of the surfaces of the second conductive pillars 15 exposed from the second insulating layer 16 and serving as solder ball pads. The surface processing layer 17 is formed on the exposed surfaces of the first wiring layer 11 and the second conductive pillars 15.
However, in the method of fabricating the conventional interposer substrate 1, the surface processing layers 17 and 17′ are made of an organic solderability preservative (OSP), which are not suitable to be used for products wherein the solder pads (i.e., the second conductive pillars 15) must be exposed under normal circumstances, such as in land grid array (LGA).
If the surface processing layer 17 of the solder pads is made of ENEPIG or Ni/Au, the following problems will occur.
First, it is required to select the process (i.e., to perform two surface processing processes, one with forming the surface processing layer 17 with OSP, the other with forming the surface processing layer 17 with ENEPIG or Ni/Au, which requires covering with resist layer during the process, thereby causing precipitation of the resist material, and resulting in poor reliability.
Second, it is difficult to control the intermetallic compound (IMC) and a problem of nickel barrier may occur.
Hence, there is an urgent need to solve the foregoing problems encountered in the prior art.